32-bit RX CPU core

? Max. operating frequency: 40 MHz

Capable of 65.6 DMIPS in operation at 40 MHz

? Enhanced DSP: 32-bit multiply-accumulate and 16-bit

multiply-subtract instructions supported

? Built-in FPU: 32-bit single-precision floating point

(compliant to IEEE754)

? Divider (fastest instruction execution takes two CPU clock

cycles)

? Fast interrupt

? CISC Harvard architecture with 5-stage pipeline

? Variable-length instructions, ultra-compact code

? On-chip debugging circuit

? Memory protection unit (MPU) supported

■ Low power design and architecture

? Operation from a single 2.7-V to 5.5-V supply

? Three low power consumption modes

■ On-chip code flash memory, no wait states

? 128-/64-Kbyte capacities

? On-board or off-board user programming

■ On-chip SRAM, no wait states

? 12 Kbytes of SRAM

■ DMA

? DTC: Four transfer modes

■ Reset and supply management

? Seven types of reset, including the power-on reset (POR)

? Low voltage detection (LVD) with voltage settings

■ Clock functions

? Main clock oscillator frequency: 1 to 20 MHz

? External clock input frequency: Up to 20 MHz

? PLL circuit input: 4 MHz to 12.5 MHz

? On-chip low-speed oscillator, on-chip high-speed

oscillator, dedicated on-chip oscillator for the IWDT

? Clock frequency accuracy measurement circuit (CAC)

■ Independent watchdog timer

? 15-kHz on-chip oscillator produces a dedicated clock

signal to drive IWDT operation.

■ Useful functions for IEC60730 compliance

? Self-diagnostic and disconnection-detection assistance

functions for the A/D converter, clock frequency accuracy

measurement circuit, independent watchdog timer, RAM

test assistance functions using the DOC, etc.

■ MPC

? Multiple locations are selectable for I/O pins of peripheral

functions